1. Field of the Invention
This invention relates to a structure of metallization, and more particularly, to an anti-oxidation structure for the top copper layer.
2. Description of Related Art
As the requirement on the complexity and precision of an integrated circuit design keeps increasing in order to reduce the feature size of a semiconductor device and increase the integration of an integrated circuit, a semiconductor device has to contain more than two metal layers to achieve the fabrication of high-density metal interconnects on a limited surface of a chip. Conventionally, aluminum is used as the material of a metal layer. However, as the design rules of a semiconductor device get finer and higher, the requirements of lower resistivity and higher reliability increase as well. Since copper has better conductivity and reliability than that of aluminum, copper has become a new material used in the metal layers.
FIGS. 1A through 1C are the cross-sectional views showing conventional metallization process. Referring to FIG. 1A, a number of copper interconnects are formed on a provided semiconductor substrate 10, wherein the semiconductor substrate 10 has some pre-formed devices, such as a transistor (not shown). A multi-interconnect layer 12 is used here to represent all formed copper interconnects. A top copper layer 14 is formed on the top of the multi-interconnect layer 12, and is surrounded by insulation layer 13.
Referring next to FIG. 1B, an insulation film 16 is deposited on the top of the top copper layer 14, preferably by a chemical vapor deposition (CVD) process, wherein the insulation film includes SiN or SiON. Then, a passivation layer 18 is formed on top of the insulation film 16, wherein the passivation layer 18 includes borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), spin-on glass (SOG), or other dielectric materials. The preferable method for forming the passivation layer 18 is also a CVD process.
Referring to FIG. 1C, the passivation 18 and the insulation film 16 are patterned and etched through in sequence by a photolithography process and an etching process for forming a pad window 19 to expose the top copper layer 14.
The foregoing fabrication process for a top copper layer 14 tends to manifest an occurrence of oxidation on the copper layer before or during the next welding process for connecting the top copper layer to a bonding pad, because the top copper layer 14 is exposed to the air. The oxidation of copper decreases the conductivity and the reliability of a copper interconnect, and further causes a short that might possibly damage the whole integrated circuit.